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ISL24011
Octal Voltage Level Shifter for TFT/LCD Panels
Data Sheet October 21, 2005 FN6196.0
High Voltage TFT-LCD Logic Driver
The ISL24011 is a high voltage TFT-LCD logic driver with +40V and -20V output voltage swing capability. It is manufactured using Intersil's proprietary monolithic high voltage bipolar process and is capable of driving a 4700pF load in 500ns. The ISL24011 will level shift a digital input signal to an output voltage nearly equal to its output supply voltages. The ISL24011 has 3 supplies. VON1 and VON2 are positive supplies with a voltage range between +10V and +40V. VOFF is the negative supply with a voltage range between -5V and -20V. Outputs 1 through 6 are connected to VON1 and VOFF. Outputs 7 and 8 are connected to VON2 and VOFF. This configuration enables outputs 1 through 6 to provide slicing to the row drivers to reduce flicker, and outputs 7 and 8 to control possible supply lines. VON2 should remain constant. It is possible to tie VON1 and VON2 supplies together, if independent control as described above is not desired. VON2 is required to be greater than or equal to VON1 at all times. The ISL24011 is available in a 20 Ld TSSOP package. It is specified for operation over the -40C to +85C industrial temperature range.
Features
* 0V to 5.5V Input Voltage Range * +40V and -20V Output Voltage Range * 10mA Output Continuous Current (all 8 channels) * 25mA Output Peak Current (all 8 channels) * Rise/Fall Times 260ns/290ns * Propagation Delay 230ns * 50kHz Input Logic Frequency * 20 Ld TSSOP Pb-Free Package * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* TFT-LCD panels
Pinout
ISL24011 (20 LD TSSOP) TOP VIEW
GND IN1 IN2 IN3 1 2 3 4 5 6 7 8 9 20 VON1 19 OUT1 18 OUT2 17 OUT3 16 OUT4 15 OUT5 14 OUT6 13 OUT7 12 OUT8 11 VON2
Ordering Information
PART NUMBER ISL24011IVZ (Note) PART TEMP. MARKING RANGE (C) 24011IVZ -40 to +85 -40 to +85 PACKAGE PKG. DWG. #
IN4 IN5 IN6 IN7 IN8
20 Ld TSSOP M20.173 (Pb-free) 20 Ld TSSOP M20.173 (Pb-free) Tape & Reel
ISL24011IVZ-T 24011IVZ (Note)
VOFF 10
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL24011 Functional Diagram
CONNECTED TO VON1 IN1 AND VOFF OUT1
CH1
OUT2 CH2 IN2 OUT3 IN3 CH3 OUT4 IN4 CH4 OUT5 CH5 IN5 OUT6 IN6 CH6
CONNECTED TO VON2 IN7 AND VOFF
CH7
OUT7
CH8 IN8
OUT8
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FN6196.0 October 21, 2005
ISL24011
Absolute Maximum Ratings (TA = 25C)
Driver Positive Supply Voltage Range, (VON) . . . . . . . . +5V to +40V Power Supply Voltage Range, (VON to VOFF). . . . . . . +10V to +60V Negative Supply Voltage Range, (VOFF) . . . . . . . . . . . . . -20V to -5V Supply Turn-On Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/s Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . -0.5V to 5.5V Output Voltage Range, All Outputs . . . . . VOFF -0.5V to VON +0.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140 IOUT (continuous, all 8 channels . . . . . . . . . . . . . . . . . . . . . . . 80mA TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +150C TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a HIGH effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VON = 22V, VOFF = -5V, TA = -40C to +85C Unless Otherwise Specified. Typical values tested at 25C CONDITION MIN -5 (VOFF) 5.0 TYP MAX 22 (VON) 8.0 UNIT V mA
DESCRIPTION
Power Supplies Recommended Operating Voltages I(VON) Supply Current All Inputs low or high No load VON = VON1 + VON2 All Inputs low or high No load Each Input low or high High = 1.8V, Low = 0.8V IOH = -100A VON = 22V RL = 4700pF in parallel with 5k IOH = +100A VOFF = -5V RL = 4700pF in parallel with 5k
I(VOFF) IIN VOH
Supply Current Input Leakage High Level Output Voltage
-8.0 -10 (VON - 1.5V)
-5.0
mA 10 A V
3.5
21.2
VOL
Low Level Output Voltage
-4.3
(VOFF + 1.5V)
V
VIH VIL tplh
High Level Input Voltage Low Level Input Voltage Low to High Prop Delay 50% to 50%, Tested with RL = 4700pF in parallel with 5k, f = 50kHz Measured at 50% to 50% f = 50kHz RL = 4700pF in parallel with 5k Measured at 10% to 90% f = 50kHz RL = 4700pF in parallel with 5k Measured at 10% to 90% f = 50kHz RL = 4700pF in parallel with 5k
1.8 0.8 190 400
V V ns
tphl
High to Low Prop Delay
230
400
ns
ttlh
Rise Time
260
400
ns
tthl
Fall Time
290
500
ns
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FN6196.0 October 21, 2005
ISL24011 Pin Descriptions
PIN NUMBER TSSOP-20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME GND IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 VOFF VON2 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VON1 EQUIVALENT CIRCUIT 4 1 1 1 1 1 1 1 1 4 4 3 3 2 2 2 2 2 2 4 Ground pin Level shifter input 1 Level shifter input 2 Level shifter input 3 Level shifter input 4 Level shifter input 5 Level shifter input 6 Level shifter input 7 Level shifter input 8 Negative output supply for all channels Positive output supply for channels 7 and 8. VON2 is required to be greater than or equal to VON1 Lever shifter output 8 Lever shifter output 7 Lever shifter output 6 Lever shifter output 5 Lever shifter output 4 Lever shifter output 3 Lever shifter output 2 Lever shifter output 1 Positive output supply for channels 1 through 6. VON1 is required to be less than or equal to VON2
VON1 OUT VOFF OUTPUTS 1-6 VOFF VON2 OUT VOFF
DESCRIPTION
VON2 IN
OUTPUTS 7-8
CIRCUIT 1.
VON2 VON1 VOFF
CIRCUIT 2.
CIRCUIT 3.
ESD CLAMP
GND
CIRCUIT 4.
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FN6196.0 October 21, 2005
ISL24011 Typical Performance Curves TA = 25C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified.
25.0 22.5 20.0 17.5 15.0 (mA) 12.5 10.0 7.5 5.0 2.5 0.0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 VON2 VON1 (mA) VON1 & VON2 = 22V VOFF = -5V INPUT 50% DUTY CYCLE VOFF 60.0 54.0 48.0 42.0 36.0 30.0 24.0 18.0 12.0 6.0 0.0 10 15 20 25 30 35 40 45 50 55 60 VON2 65 70 75 VON1 & VON2 = 22V VOFF = -5V INPUT 50% DUTY CYCLE VON1 VOFF
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 1. SUPPLY CURRENT vs FREQUENCY 1 CHANNEL TOGGLING
FIGURE 2. SUPPLY CURRENT vs FREQUENCY 4 CHANNELS TOGGLING
80.0 72.0 64.0 56.0 48.0 (mA) (mA) 40.0 32.0 24.0 16.0 8.0 0.0 10 15 20 25 30 35 40 45 50 55 60 VON2 65 70 75 VOFF VON1 & VON2 = 22V VOFF = -5V INPUT 50% DUTY CYCLE VON1
100.0 90.0 80.0 70.5 60.0 50.0 40.0 30.0 20.0 10.0 0.0 10 15 20 25 30 35 40 45 50 55 60 VON2 65 70 75 VOFF VON1 & VON2 = 22V VOFF = -5V INPUT 50% DUTY CYCLE VON1
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 3. SUPPLY CURRENT vs FREQUENCY 6 CHANNELS TOGGLING
FIGURE 4. SUPPLY CURRENT vs FREQUENCY 8 CHANNELS TOGGLING
500 450 400 350 300 (ns) 250 200 150 100 50 0 10 12 15 17 19 22 24 26 28 31 33 35 38 40 PROP DELAY VON1 & VON2 = 10-40V VOFF = -5V 50kHz 10% DUTY CYCLE FALL TIME RISE TIME (ns)
500 450 400 350 300 250 200 150 100 50 0 10 VON1 & VON2 = 10-40V VOFF = -20V 50kHz 10% DUTY CYCLE 12 15 17 19 22 24 26 28 31 33 35 38 40 VON1 & VON2 (V) PROP DELAY FALL TIME RISE TIME
VON1 & VON2 (V)
FIGURE 5. RISE TIME, FALL TIME AND PROP DELAY vs VON1 & VON2 VOLTAGE WITH VOFF = -5V
FIGURE 6. RISE TIME, FALL TIME AND PROP DELAY vs VON1 & VON2 VOLTAGE WITH VOFF = -20V
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FN6196.0 October 21, 2005
ISL24011 Typical Performance Curves TA = 25C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified. (Continued)
400 360 320 280 240 (ns) 200 160 120 80 40 0 10 12 15 17 19 22 24 26 1800pF VON1 & VON2 = 10-40V VOFF = -5V 50kHz 10% DUTY CYCLE 28 31 33 35 38 40 VON1 & VON2 (V) 4700pF (ns) 3300pF 500 450 400 350 300 250 200 150 100 50 VON1 & VON2 = 10-40V VOFF = -20V 26 28 31 33 35 38 40 1800pF 3300pF 4700pF
50kHz 10% DUTY CYCLE 0 10 12 15 17 19 22 24
VON1 & VON2 (V)
FIGURE 7. RISE TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V
FIGURE 8. RISE TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V
400 360 320 280 240 (ns) 200 160 120 80 40 0 VON1 & VON2 = 10-40V VOFF = -5V 50kHz 10% DUTY CYCLE 10 12 15 17 19 22 24 26 28 31 33 35 38 40 VON1 & VON2 (V) 1800pF 4700pF (ns) 3300pF
500 450 400 350 300 250 200 150 100 50 0 10 VON1 & VON2 = 10-40V VOFF = -20V 50kHz 10% DUTY CYCLE 12 15 17 19 22 24 26 28 31 33 35 38 40 VON1 & VON2 (V) 1800pF 3300pF 4700pF
FIGURE 9. FALL TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V
FIGURE 10. FALL TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V
300 270 240 210 180 (ns) 150 120 90 60 30 VON1 & VON2 = 10-40V VOFF = -5V 26 28 31 33 35 38 40 4700pF 3300pF (ns) 1800pF
300 270 240 210 180 150 120 90 60 30 0 VON1 & VON2 = 10-40V VOFF = -20V 50kHz 10% DUTY CYCLE 10 12 15 17 19 22 24 26 28 31 33 35 38 40 VON1 & VON2 (V) 4700pF 3300pF 1800pF
50kHz 10% DUTY CYCLE 0 10 12 15 17 19 22 24
VON1 & VON2 (V)
FIGURE 11. PROP DELAY vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V
FIGURE 12. PROP DELAY vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V
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FN6196.0 October 21, 2005
ISL24011 Typical Performance Curves TA = 25C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified. (Continued)
2V/DIV PULSE INPUT
0 1800pF
4700pF
5V/DIV
0
VON1 & VON2 = 22V VOFF = -5V 50kHz 10% DUTY CYCLE 400ns/DIV
FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE
Application Information
General
The ISL24011 is an octal voltage level shifter. The part was designed to level shift a digital input signal to +22V and -5V for TFT-LCD displays and is capable of level shifting input logic signals (0V to 5.5V) to outputs as large as +40V and -20V.
Latch-up Proof
The ISL24011 is manufactured in a high voltage DI process that isolates every transistor in its own tub making the part latch-up proof.
Input Pin Connections
Unused inputs must be tied to ground. Failure to tie unused input pins to ground will result in rail to rail oscillations on the respective output pins and higher unwanted power dissipation in the part. Under these conditions, the temperature of the part could get very hot.
Power Supply Decoupling
The ISL24011 requires a 1.0F decoupling capacitor as close to the VON1, VON2 and VOFF power supply pins, as possible, for a large load equal to 5k in parallel with 4700pF (Figure 16). This will reduce any dv/dt between the different supplies and prevent the internal ESD clamp from turning on and damaging the part. For lighter loads such as a series 200 resistor and a 3300pF capacitance, the decoupling capacitors can be reduced to 0.47F.
Limiting the Output Current
No output short circuit current limit exists on this part. All applications need to limit the output current to less than 80mA. Adequate thermal heat sinking of the parts is also required.
Application Diagram (TV)
DC/DC CONVERTER 1.0F
Power Supply Sequence
The ISL24011 requires that VON2 be greater than or equal to VON1 at all times. Therefore, if VON1 and VON2 are different supplies, then VON2 needs to be turned on before VON1. The reason for this requirement is shown in Circuit 4 in the Pin Description Table. The ESD protection diode between VON2 and VON1 will forward bias if VON1 becomes a diode drop greater than VON2. Recommended power supply sequence: VON2, VON1, VOFF, then input logic signals. The ESD protection scheme is based on diodes from the pins to the VON2 supply and a dv/dt-triggered clamp. This dv/dt-triggered clamp imposes a maximum supply turn-on slew rate of 10V/s. This clamp will trigger if the supply powers up too fast, causing amps of current to flow. Ground and VON1 are treated as I/O pins with this protection scheme. In applications where the dv/dt supply ramp could exceed 10V/s, such as hot plugging, additional methods should be employed to ensure the rate of rise is not exceeded. 7
VON1 VON2
VOFF 1.0F
1.0F
TIMING CONTROLLER
ISL24011 LEVEL SHIFTER
LCD PANEL
FIGURE 14. TYPICAL TV APPLICATION CIRCUIT
FN6196.0 October 21, 2005
ISL24011 Application Diagram (Monitor)
DC/DC CONVERTER VOFF VON1 VON SLICER CIRCUIT 1.0F C1 1.0F C2
Test Circuit
VON1 VON2
VON2
IN1
ISL24011
OUT1
1.0F
VOFF VON2
VON1 1.0F
IN8
OUT8
5k
4700pF
1.0F
VOFF TIMING CONTROLLER ISL24011 LEVEL SHIFTER LCD PANEL
1.0F
C3
If the output load is a series 200 resistor and a 3300pF then C1, C2 and C3 can be reduced to 0.47pF.
INx tPLH tPHL
FIGURE 15. TYPICAL MONITOR APPLICATION CIRCUIT WITH SLICER TO REDUCE FLICKER
OUTx
tR
tF
FIGURE 16. TEST LOAD AND TIMING DEFINITIONS
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FN6196.0 October 21, 2005
ISL24011 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 NOTES 9 3 4 6 7 8o Rev. 1 6/98
A1 0.10(0.004) A2 c
e
b 0.10(0.004) M C AM BS
E1 e E L N
0.026 BSC 0.246 0.0177 20 0o 8o 0.256 0.0295
0.65 BSC 6.25 0.45 20 0o 6.50 0.75
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6196.0 October 21, 2005

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